The invention relates to a test facility for testing the unit wherein signals are transmitted via input pins and response signals are received on output pins.
Such a test facility is known from U.S. Pat. No. 4,399,405, incorporated herein by reference, containing a transmitter and a receiver for each pin to be tested. The transmitter generates a test signal which is supplied to an input pin of a unit under test, for example a printed circuit board. In response thereto, the unit under test emits at another output pin a response signal which depends on the structure of the unit under test. The response signal is supplied to one of the receivers in the test facility which evaluates it. The test facility can have a plurality of transmitters, receivers, and test pins, with each test pin having one transmitter and one receiver allocated to it.
The test signals generated by the test facility for simultaneous input at input pins of the unit under test generally exhibit a chronological or timewise offset which depends on the the structure of the test facility. In other words, the plurality of test signals are not always generated at the same point in time, but rather their appearance fluctuates around a desired appearance time. When, for example, printed circuit boards which contain modules in TTL, MOS or ECL technology are tested with the assistance of such a test facility, the test facility must achieve a chronological offset of the test signals which is .ltoreq..+-.10 ns. The test facility must be accordingly designed.
When such a test facility is to be employed for testing units under test which require a smaller chronological offset, for example .ltoreq..+-.100 ps, then the overall test facility would have to be modified.
An object underlying the invention is to specify a system which adapts an existing test facility having a fixed, chronological or time-wise offset of the plurality of test signals input to a unit under test for which a smaller time offset of the test signals being input relative to a given time point is necessary while testing. Given an arrangement of the type initially specified, this object is achieved in that a transmitter and a receiver are connected in anti-parallel relationship with respect to one another between each of the test pins and the respective input/output of the unit under test, said transmitter and receiver being alternately engageable depending upon whether the test facility pin is an input or output. A second clock signal derived from a first clock signal can be applied to the transmitter. It is used to control a connection through of the test signal at the input of the transmitter to its output. A third clock signal can be applied to the receiver. It is used to control a connection through of the response signal at the input to the output thereof given upward movement of a reference voltage. A time-lag circuit is provided to which a first clock signal is supplied and which generates the second and the third clock signals at an adjustable chronological interval.
When the transmitter or receiver of the arrangement are constructed in ECL technology, then the cut-in arrangement for the receiver or transmitter can consist of a transistor whose emitter is connected to the operating potential terminal of the output stage of the sender/receiver, whose base terminal lies at a first fixed potential over a diode, and to which a control voltage between the first potential and a potential switching the transistor conductive is supplied.
In order to achieve a tri-state character for the receiver/transmitter, the output stage constructed as an emitter follower is connected to a second fixed potential over a resistor.
A further cut-in arrangement for the transmitter/receiver can comprise a respective NOR element connected to the output of the transmitter and receiver, a change-over signal being supplied to its other input either directly or over an inverter. The tri-state character can be achieved in that the other input of the NOR element following the transmitter is connected to a fixed potential over a resistor.